Design a Differential Amplifier Using 2 Bjt

Download

Skip this Video

Loading SlideShow in 5 Seconds..

Chapter 6 Differential and Multistage Amplifiers PowerPoint Presentation

Chapter 6 Differential and Multistage Amplifiers

Download Presentation

Chapter 6 Differential and Multistage Amplifiers

- - - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript

---

1. Chapter 6 Differential and Multistage Amplifiers Introduction 6.1 The BJT differntial pair 6.2 Small-signal operation of the BJT differential amplifier 6.3 Other nonideal characteristics of the differential amplifier 6.4 MOS diffenrential amplifiers 6.5 Biasing in intergrated circuits 6.6 The BJT differential amplifier with active load 6.9 Multistage amplifiers

2. The differential amplifier (pair) configuration is the most widely used building block in analog IC design. BJT differential amplifier is the basis of a very-high-speed logic circuit family, called emitter-coupled logic (ECL). Introduction Why?

3. Reasons: Direct coupling between signal source and amplifier will easily cause temperature Drift (zero drift). What shall we do?

5. There are 2 reasons for using differential in preference to single-ended amplifiers. (1) Differential circuits are much less sensitive to noise and interference than single-ended circuits. (2) It enables us to bias the amplifier and to couple amplifier stage without the need of bypass and coupling capacitors which are impossible to fabricate economically by IC technology. Advantages

6. 6.1 The BJT Differential PairBasic Operation-1:Common-mode input • The differential pair with a common-mode input signal vCM. • Two transistors are matched. • Current source with infinite output resistance. • Current I divide equally between two transistors. • The difference in voltage between the two collector is zero. • The differential pair rejects the common-mode input signal as long as two transistors remain in active region.

7. Basic Operation-2 • The differential pair with a "large" differential input signal. • Q1 is on and Q2 is off. • Current I entirely flows in Q1.

8. Basic Operation-3 • The differential pair with a large differential input signal of polarity opposite to that in (b). • Q2 is on and Q1 is off. • Current I entirely flows in Q2.

9. Basic Operation-4:Difference-mode or Difference signals • The differential pair with a small differential input signal vi. • Small signal operation or linear amplifier. • Assuming the bias current source I to be ideal and thus I remains constant with the change in vCM. • Increment in Q1 and decrement in Q2.

10. Large-Signal Operation

11. Nonlinear curves. Linear segments. Maximum value of input differential voltages as a small-signal amplifier can be used as a fast current switch Enlarge the linear segment by including equal resistance Re in series with the emitters. Large-Signal Operation

12. Large-Signal Operation The transfer characteristics of the BJT differential pair (a) can be linearized by including resistances in the emitters.

13. 6.2 Small-signal operation of the BJT differential amplifier The currents and voltages in the differential amplifier when a small differential input signal vid is applied.

14. Small-Signal Operation A simple technique for determining the signal currents in a differential amplifier excited by a differential voltage signal vid; dc quantities are not shown.

15. Small-Signal Operation • A differential amplifier with emitter resistances. • Only signal quantities are shown (in color).

16. Input Differential Resistance • Input differential resistance is finite. The resistance seen between the two bases is equal to the total resistance in the emitter circuit multiplied by (1+β). • Input differential resistance of differential pair with emitter resistors.

17. Differential Voltage Gain • Differential voltage gain • Output voltage taken single-ended • Output voltage taken differentially

18. Differential Voltage Gain • Differential voltage gain of the differential pair with resistances in the emitter loads • Output voltage taken single-ended • Output voltage taken differentially The voltage gain is equal to the ratio of the total resistance in the collector circuit to the total resistance in the emitter circuit.

19. Differential Half-Circuit Analysis • Differential input signals. • Single voltage at joint emitters is zero. • The circuit is symmetric. • Equivalent common-emitter amplifiers in (b).

20. Differential Half-Circuit Analysis • This equivalence applies only for differential input signals. • Either of the two common-emitter amplifiers can be used to find the differential gain, differential input resistance, frequency response, and so on • Half circuit is biased at I/2. • The voltage gain(with the output taken differentially) is equal to the voltage of half circuit.

21. Differential Half-Circuit Analysis • The differential amplifier fed in a single-ended manner. • Signal voltage at the emitter is not zero. • Almost identical to the symmetric one.

22. Common-Mode Gain The differential amplifier fed by a common-mode voltage signal vicm.

23. Common-Mode Gain Equivalent "half-circuits" for common-mode calculations.

24. Common-mode voltage gain Output voltage taken single-ended Output voltage taken differentially Common-Mode Gain

25. Common-Mode Rejection Ratio • Common-mode rejection ratio • Output voltage taken single-ended • Output voltage taken differentially This is true only when the circuit is symmetric. • Mismatch on CMRR

26. Input Common-Mode Resistance • Definition of the input common-mode resistance Ricm. • The equivalent common-mode half-circuit.

27. Input common-mode resistance Input common-mode resistance is very large. Input Common-Mode Resistance

28. Example 6.1

29. Evaluate the following: The input differential resistance. The overall differential voltage gain(neglect the effect of ro). The worst-case common-mode gain if the two collector resistance are accurate within ±1%. The CMRR, in dB. The input common-mode resistance(suppose the Early voltage is 100V). Example6.1 (cont'd)

30. 6.3 Other Nonideal characteristic of the Differential Amplifier • Input offset voltage Vos Ideal differential pair is perfectly matched, but practical circuits exhibits • Mismatches that result in a dc Vo is not zero. Vo is the output dc offset • Voltage. Input offset voltage Vos: • Input bias and offset currents Ios perfectly matched • Input Common-Mode Range

31. 6.4 MOS Differential Amplifiers

32. Operation with a Common –Mode Input Voltage

33. Symmetry circuit. Common-mode voltage. Current I divides equally between two transistors. The difference between two drains is zero. The differential pair rejects the common-mode input signals. Operation with a Common –Mode Input Voltage

34. Operation with a Differential Input Voltage • The MOS differential pair with a differential input signal vid applied. • With vid positive: vGS1>vGS2, iD1>iD2, and vD1<vD2; thus (vD2-vD1) will be positive. • With vid negative: vGS1<vGS2, iD1<iD2, and vD1>vD2; thus (vD2-vD1) will be negative.

35. Differential input voltage. Response to the differential input signal. The current I can be steered from one MOS to the other by varying the differential input voltage in the range: When differential input voltage is very small, the differential output voltage is proportional to it, and the gain is high. Operation with a Differential Input Voltage

36. Large-Signal Operation • Transfer characteristic curves • Normalized plots of the currents in a MOSFET differential pair. • Note that VOV is the overdrive voltage at which Q1 and Q2 operate when conducting drain currents equal to I/2.

37. Nonlinear curves. Maximum value of input differential voltage. When vid= 0, two drain currents are equal to I/2. Linear segment. Linearity can be increased by increasing overdrive voltage(see next slide). Price paid is a reduction in gain(current I is kept constant). Large-Signal Operation

38. Large-Signal Operation The linear range of operation of the MOS differential pair can be extended by operating the transistor at a higher value of VOV.

39. Linear amplifier Differential gain Common-mode gain Common-mode rejection ratio(CMRR) Mismatch on CMRR Small-Signal Operation of MOS Differential Pair

40. Differential Gain • a common-mode voltage applied to set the dc bias voltage at the gates. • vid applied in a complementary (or balanced) manner.

41. Differential Gain Signal voltage at the joint source connection must be zero.

42. Differential Gain An alternative way of looking at the small-signal operation of the circuit.

43. Differential gain Output taken single-ended Output taken differentially Advantages of output signal taken differentially Reject common-mode signal Increase in gain by a factor of 2(6dB) Differential Gain

44. Differential Gain MOS differential amplifier with ro and RSS taken into account.

45. Differential Gain • Equivalent circuit for determining the differential gain. • Each of the two halves of the differential amplifier circuit is a common-source amplifier, known as its differential "half-circuit."

46. Differential gain Output taken single-ended Output taken differentially Differential Gain

47. Common-Mode Gain The MOS differential amplifier with a common-mode input signal vicm.

48. Common-Mode Gain • Equivalent circuit for determining the common-mode gain (with ro ignored). • Each half of the circuit is known as the "common-mode half-circuit."

49. Common-mode gain Output taken single-ended Output taken differentially Common-Mode Gain

50. Common-mode rejection ratio(CMRR) Output taken single-ended Output taken differentially This is true only when the circuit is perfectly matched. Common-Mode Rejection Ratio

Design a Differential Amplifier Using 2 Bjt

Source: https://www.slideserve.com/Faraday/chapter-6-differential-and-multistage-amplifiers

Share this post